Current sensing field-effect transistors, which are frequently referred to as sense FETs, have been used for many years in integrated circuit applications where accurate current sensing can provide information for both control and over-current protection. Sense FETs are typically constructed as a small part or transistor section of a larger, main current carrying semiconductor device. For example, in a conventional insulated-gate field-effect transistor (MOSFET) device, the sense FET may comprise a small section of the channel region of the main device. In operation, the sense FET may sample a small fraction of the channel current of the larger device, thereby providing an indication of the current flowing through the main transistor device. The sense FET and main device typically share a common drain and gate, but each has a separate source electrode which may or may not be shorted to the body region.
Sense FETs are particularly useful in many power delivery applications to provide current limit protection and accurate power delivery. In order to provide these functions the sense FET needs to maintain a constant current sensing ratio (CSR) with respect to the main high-voltage FET over a wide range of drain currents (100 mA to 10 amperes), temperature (−25° C. to 125° C.), as well as fabrication process variations and mechanical stress/packaging variations. The ratio of drain current of the main high-voltage FET (HVFET) to that of the sense FET typically ranges between 20:1 to 800:1, or greater.
Lateral field-effect transistors are widely used for high-voltage (e.g., greater than 400 volts) integrated circuit applications. In a lateral HVFET structure, a source region is laterally separated from an extended drain or drift region by a channel region. A gate structure is disposed over the channel region, insulated from the underlying semiconductor material by a thin layer of oxide. In the on-state, an appropriate voltage applied to the gate causes a lateral conduction channel to form between the source and extended drain regions, thereby allowing current to flow laterally through the device. In the off-state, the voltage on the gate is sufficiently low such that no conduction channel forms in the substrate and thus no current flows. In the off-state, the device supports a high voltage between the drain and source regions.
Among the difficulties that arise in the design of sense FET for use in a power IC with a lateral HVFET device are drain voltage debiasing and body-effect problems. Debiasing of the drain voltage can occur when the sense resistor (typically coupled between the source and ground) is a large percentage (e.g., >25%) of the sense FET resistance, resulting in a large voltage drop across the sense resistor. This raises the source voltage of the sense FET relative to the gate, thus lowering the gate to source drive of the sense FET relative to the main HVFET. Similarly, in a lateral HVFET where the body is physically connected to the substrate, the body of the sense FET needs to be separate from the source. This causes the sense FET threshold voltage to increase with current and compromises the sense FET tracking to the main HVFET device. Additionally, past attempts to physically locate the sense FET close to the main HVFET (e.g. in a shared well region) to improve tracking have been problematic since doing so can affect the charge balance in the device, resulting in a lower breakdown voltage (BV). Another disadvantage is the location of the sense element which is typically a resistor that is located some distance away from the HVFET region. This results in poor matching to the HVFET.